1. Field of Invention
Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional non-volatile memory device and a method of manufacturing the same.
2. Description of Related Art
A non-volatile memory retains data stored therein even when not powered. Two-dimensional memory devices in which memory cells are fabricated in a single layer over a silicon substrate have reached physical limits in increasing their degree of integration. Accordingly, three-dimensional (3D) non-volatile memory devices in which memory cells are stacked in a vertical direction over a silicon substrate have been proposed.
When a conventional 3D non-volatile memory device is manufactured, word lines and selection lines use the same processes and include conductive layers having the same thickness.
While the memory device is being driven, a bias appropriate for a program or erase operation needs to be applied to the selection lines. In addition, leakage current of the selection transistors needs to be reduced in order to prevent program interference. However, leakage current nay be difficult to control with the selection lines having the same thickness as the word lines.
Therefore, a method of stacking a plurality of selection transistors one on top of another has been conventionally used to control leakage current of selection transistors. According to this method, a single string includes a plurality of drain selection transistors and a plurality of source selection transistors.
However, if the number of selection transistors stacked on top of one another increases, processes such as an etch process for forming a channel hole and an etch process for forming a contact pad may become more difficult. In addition, an increase in the area of the contact pad may impose limitations in improving a degree of integration of a memory device.